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V103A
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
General Description
The V103A LVDS display interface transmitter is primarily designed to support pixel data transmission between a video processing engine and a digital video display. The data rate supports up to SXGA+ resolutions and can be used in Plasma, Rear Projector, Front Projector, CRT and LCD display applications. It can also be used in other high-bandwidth parallel data applications and provides a low EMI interconnect over a low cost, low bus width cable up to several meters in length. The V103A converts 35 bits of CMOS/TTL data, clocked on the rising or falling edge of an input clock (selectable), into six LVDS (Low Voltage Differential Signaling) serial data stream pairs. In video applications the 35 bits is normally divided into 10 bits for each R, G and B channel and 5 control bits. When combined with the V104 LVDS display interface receiver, the V103A + V104 combination provides a 35-bit wide, 90 MHz transport. The rate of each LVDS channel is 630 Mbps for a 90MHz data input clock, 945 Mbps for 135MHz.
Features
* Pin compatible with THine THC63LVD103 * Wide pixel clock range: 8 - 135 MHz * Guaranteed operation over -20 to +85 C ambient
temperature
* Supports a wide range of video and graphics modes
including VGA, SVGA, XGA, SXGA, SXGA+, NTSC, PAL, SDTV, and HDTV up to 1080I or 720P
* Internal PLL requires no external loop filter * Selectable rising or falling clock edge for data
alignment
* Compatible with Spread Spectrum clock source * Reduced LVDS output voltage swing mode
(selectable) to minimize EMI
* CMOS/TTL data inputs can be configured for
reduced input voltage swing
* * * *
Single 3.3 V supply Low power consumption CMOS design Power down mode 64-pin TQFP lead free package
Block Diagram
TA0-6 TB0-6 TC0-6 TD0-6 TE0-6 RS R/F /PWDN
7 7 7 7 7
TA+ TATB+ TBParallel to Serial TC+ TCTD+ TDTE+ TE-
CLKIN (8 to 135 MHz)
PLL
TCLK+ TCLK-
V103A Datasheet
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11/18/05
Revision 3.2
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 * t e l ( 4 0 8) 2 97 - 1 2 0 1 * w ww. i c s t . co m
V103A
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
Pin Assignment
TD4 TD3 TD2 TD1 R/F TD0 TC6 TC5 GND TC4 TC3 TC2 TC1 VCC TC0 TB6 TD5 GND TD6 TE0 TE1 TE2 VCC TE3 TE4 GND TE5 CLKIN /PWDN PLLGND PLLVCC TE6 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64-pin TQFP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
TB5 GND TB4 TB3 TB2 RS TB1 TB0 TA6 GND TA5 TA4 TA3 TA2 TA1 TA0
V103A Datasheet
LVDSGND TE+ TETD+ TDTCLK+ TCLKTC+ TCLVDSGND LVDSVCC TB+ TBTA+ TALVDSGND
2
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
11/18/05
Revision 3.2
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 * t e l ( 4 0 8) 2 97 - 1 2 0 1 * w ww. i c s t . co m
V103A
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
Pin Descriptions
Pin Number
30, 31 28, 29 24, 25 20, 21 18, 19 22, 23 33, 34, 35, 36, 37, 38, 40 41, 42, 44, 45, 46, 48, 49 50, 52, 53, 54, 55, 57, 58 59, 61, 62, 63, 64, 1, 3 4, 5, 6, 8, 9, 11, 16 13 43 60 51, 7 12 2, 10, 39, 47, 56 27 17, 26, 32 15 14
Pin Name
TA+, TATB+, TBTC+, TCTD+, TDTE+, TETCLK+, TCLKTA0 ~ TA6 TB0 ~ TB6 TC0 ~ TC6 TD0 ~ TD6 TE0 ~ TE6 /PWDN RS R/F VCC CLKIN GND LVDSVCC LVDSGND PLLVCC PLLGND
Pin Type
Pin Description
LVDS OUT
LVDS Serial Data Output Pairs
LVDS OUT
LVDS Reference Clock Output Pair
IN
CMOS/TTL (or small signal) Data Bit Inputs
IN IN IN Power IN Ground Power Ground Power Ground
High: Normal device operation Low: Power down; all outputs become high impedance Voltage level on this pin sets LVDS output swing voltage and data input swing voltage; refer to the table at the bottom of this page. Input Clock triggering edge select. High: Rising edge; Low: Falling edge. Power supply pins for TTL inputs and digital circuitry. Clock Input. Ground pins for TTL inputs and digital circuitry. Power supply pins for LVDS outputs. Ground pins for LVDS outputs. Power supply pin for PLL circuitry. Ground pin for PLL circuitry.
RS Input Voltage Configuration to set LVDS Output Swing and Data Input Swing RS Input Voltage
VCC 0.6 ~ 1.4 V (VREF1) GND
LVDS Output Swing
350 mV 350 mV 200 mV
CMOS/TTL Input Configuration (Input Voltage Swing)
Standard Configuration1 Small Input Swing Configuration1 Standard Configuration1
Note 1: Refer to DC Electrical Characteristics.
V103A Datasheet
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11/18/05
Revision 3.2
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 * t e l ( 4 0 8) 2 97 - 1 2 0 1 * w ww. i c s t . co m
V103A
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
External Components
Decoupling capacitors should be used for all power pins. The V103A requires no other external components.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the V103A. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VCC CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Driver Output Voltage Storage Temperature Junction Temperature Soldering Temperature (10 seconds) Maximum Power Dissipation @ 25C -0.3 V to +4.0 V -0.3 V to VCC+0.3 V -0.3 V to VCC+0.3 V -0.3 V to VCC+0.3 V -55 to +150C 120C 260C 1.0 W
Rating
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND)
Min.
-20 +3.0
Typ.
+3.3
Max.
+85 +3.6
Units
C V
V103A Datasheet
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11/18/05
Revision 3.2
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 * t e l ( 4 0 8) 2 97 - 1 2 0 1 * w ww. i c s t . co m
V103A
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
DC Electrical Characteristics
VDD=3.3 V 10%, Ambient temperature -20 to +85C
Parameter
Input High Voltage Input Low Voltage Input Current Max Input Swing Voltage Input Reference Voltage into pin RS High Level Input Voltage (for small input swing condition) Low Level Input Voltage (for small input swing condition)
Symbol
VIH VIL IINC VDDQ1 VREF VSH2 VSL2
Conditions
RS=VCC or GND RS=VCC or GND 0VMin.
2.00 GND
Typ.
Max.
VCC 0.80 10
Units
V V A V V V
CMOS/TTL Inputs, Standard Configuration
CMOS/TTL Inputs, Small Input Swing Configuration VREF = VRS = VDDQ/2 VREF=VDDQ/2 VREF=VDDQ/2 1.2 VDDQ/2 VDDQ/2 +0.1V VDDQ/2 -0.1V 2.8
V
Note 1: VDDQ voltage defines the max voltage of the small swing input and is not an actual input into the device. Note 2: Small input swing voltage is applied to TA[6:0], TB[6:0], TC[6:0], TD[6:0], TE[6:0], and CLKIN. LVDS Transmitter DC Specifications Differential Output Voltage, RL = 100 VOD Normal swing RS = VCC Reduced swing RS = GND Change in VOD Between Complimentary Output States Common Mode Voltage Change in VOC Between Complimentary Output States Output Short Circuit Current Output Tri-State Current DVOD VOC DVOC IOS IOZ VOUT = 0V, RL = 100 /PWDN = 0V, VOUT = 0V to VCC RL = 100 1.125 1.250 250 100 350 200 450 300 35 1.375 35 -24 10 mV mV mV V mV mA A
Supply Current Transmitter Supply Current ITCCG RL = 100, CL=5 pF, VCC = 3.3 V, RS = VCC Gray Scale Pattern RL = 100, CL=5 pF, VCC = 3.3 V, RS = GND Gray Scale Pattern Transmitter Supply Current ITCCW RL = 100, CL = 5 pF, VCC = 3.3 V, RS = VCC Worst Case Pattern RL = 100, CL= 5 pF, VCC = 3.3 V, RS = GND Worst Case Pattern Transmitter Power Down Supply Current ITCCS /PWDN = L f = 85 MHz f =135 MHz f = 85 MHz f =135 MHz f = 85 MHz f =135 MHz f = 85 MHz f =135 MHz 58 70 44 56 69 87 55 73 64 76 50 62 75 93 61 79 10 mA mA mA mA mA mA mA mA A
V103A Datasheet
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11/18/05
Revision 3.2
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 * t e l ( 4 0 8) 2 97 - 1 2 0 1 * w ww. i c s t . co m
V103A
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
Gray Scale Pattern
CLKIN Tx 0
Tx 1
Tx 2
Tx 3
Tx 4
Tx 5
Tx 6
x = A, B, C, D, E
Worst Case Pattern
CLKIN Tx0
Tx1
Tx2
Tx3
Tx4
Tx5
Tx6
x = A, B, C, D, E
V103A Datasheet
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11/18/05
Revision 3.2
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 * t e l ( 4 0 8) 2 97 - 1 2 0 1 * w ww. i c s t . co m
V103A
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
AC Electrical Characteristics
VDD=3.3 V 10%, Ambient temperature -20 to +85C
Parameter
Switching Characteristics CLK IN Transition Time CLK IN Period CLK IN High Time CLK IN Low Time CLK IN to TCLK Delay TTL Data Setup to CLK IN TTL Data Hold from CLK IN LVDS Transition Time Output Data Position0 Output Data Position1 tTCIT tTCP tTCH tTCL tTCD tTS tTH tLVT tTOP1 tTOP0 -0.2 tTCP -0.2 7 2.5 0 0.6 0.0 tTCP 7 1.5 0.2 tTCP +0.2 7 ns t 2 TCP -0.2 7 t 2 TCP 7 t 2 TCP +0.2 7 ns t 3 TCP -0.2 7 t 3 TCP 7 t 3 TCP +0.2 7 ns t 4 TCP -0.2 7 t 4 TCP 7 t 4 TCP +0.2 7 ns t 5 TCP -0.2 7 t 5 TCP 7 t 5 TCP +0.2 7 ns t 6 TCP -0.2 7 t 6 TCP 7 t 6 TCP +0.2 7 10.0 ms 7.4 0.35tTCP 0.35tTCP 0.5tTCP 0.5tTCP 3tTCP 5 125.0 0.65tTCP 0.65tTCP ns ns ns ns ns ns ns ns ns ns
Symbol
Min.
Typ.
Max.
Units
Output Data Position2
tTOP6
Output Data Position3
tTOP5
Output Data Position4
tTOP4
Output Data Position5
tTOP3
Output Data Position6
tTOP2
Phase Lock Loop Set
tTPLL
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
53 40 33 8
Max.
Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
JC
V103A Datasheet
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11/18/05
Revision 3.2
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 * t e l ( 4 0 8) 2 97 - 1 2 0 1 * w ww. i c s t . co m
V103A
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
AC Timing Diagrams
TTL Input
10% CLK IN tTCIT
90%
90% 10% tTCIT
LVDS Output
VDIFF = (TA+) - (TA-) TA+ 5 pF TA100 ohms 20% tLVT
80%
80% 20% tLVT
TTL Inputs
tTCH CLK IN
VCC/2
tTCP
VCC/2
VCC/2
tTCL tTS Tx0-Tx6
VCC/2
tTH
VCC/2
tTCD TCLK+
VOC
TCLKNote: CLK IN: for R/F = GND, denote as solid line. for R/F = VCC, denote as dashed line
V103A Datasheet
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11/18/05
Revision 3.2
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 * t e l ( 4 0 8) 2 97 - 1 2 0 1 * w ww. i c s t . co m
V103A
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
Small Swing Inputs
tTCH CLK IN VDDQ/2
tTCP
VDDQ/2 tTCL tTS tTH
VDDQ/2
VREF
VDDQ GND
VDDQ Tx0-Tx6 VDDQ/2 VDDQ/2
VREF
GND tTCD TCLK+ VOC TCLKNote: CLK IN: for R/F = GND, denote as solid line. for R/F = VCC, denote as dashed line
LVDS Output
VDIFF = 0V TCLK OUT (Differential) TA+/TA6 TA5 TA4 TA3 TA2
VDIFF = 0V
TA1
TA0
TB+/-
TB6
TB5
TB4
TB3
TB2
TB1
TB0
TC+/-
TC6
TC5
TC4
TC3
TC2
TC1
TC0
TD+/-
TD6
TD5
TD4
TD3
TD2
TD1
TD0
TE+/-
TE6
TE5
TE4
TE3
TE2
TE1
TE0
Previous Cycle tTOP1 tTOP0 tTOP6 tTOP5 tTOP4 tTOP3 tTOP2
Next Cycle
V103A Datasheet
9
11/18/05
Revision 3.2
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 * t e l ( 4 0 8) 2 97 - 1 2 0 1 * w ww. i c s t . co m
V103A
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
Phase Lock Loop Set Time
2.0 V /PWDN 3.0 V 3.6 V
tTPLL
VCC
CLKIN VDIFF = 0V TCLKx+/-
V103A Datasheet
10
11/18/05
Revision 3.2
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 * t e l ( 4 0 8) 2 97 - 1 2 0 1 * w ww. i c s t . co m
V103A
TRIPLE 10-BIT LVDS TRANSMITTER FOR VIDEO
Package Outline and Package Dimensions (64-pin TQFP)
Package dimensions are kept current with JEDEC Publication No. 95, variation ACD.
SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc MIN/MAX 64 -- / 1.20 0.05 / 0.15 0.95 / 1.05 0.17 / 0.27 0.09 / 0.20 12.00 BASIC 10.00 BASIC 7.50 Ref. 12.00 BASIC 10.00 BASIC 7.50 Ref. 0.50 BASIC 0.45 / 0.75 0 / 7 -- / 0.08 -
ALL DIMENSIONS ARE IN MILLIMETERS.
D3&E3
Ordering Information
Part / Order Number V103AYLF V103AYLFT Marking V103AYLF V103AYLF Shipping Packaging
Tray (160 units per tray) Tape and Reel
Package
64-pin TQFP 64-pin TQFP
Temperature
-20 to +85 C -20 to +85 C
The "LF" part number suffix denotes the device as Lead (Pb) Free and that the device is RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
V103A Datasheet
11
11/18/05
Revision 3.2
I n t e g r a t e d C i r c u i t S y s t e m s * 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 * t e l ( 4 0 8) 2 97 - 1 2 0 1 * w ww. i c s t . co m

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